“Introduction to Power/Signal Integrity Simulation for EMC Design” Prof. Hideki Asai

With the progress of system integration, a variety of serious noise problems have occurred in the chip, package and board design and packaging. It is well-known that simulation-based design is very useful for achieving a short turnaround time (TAT), instead of an actual trial production. Therefore, in order to cope with the noise problems, signal integrity (SI), power integrity (PI) and electromagnetic interference (EMI) simulation technology is very significant. In this presentation, first, high-speed digital design issues, namely, power/signal integrity problems, are described. Next, the historical overview of the PI/SI/EMI simulation methods is described. Finally, the future trend is suggested for the overall solution for chip/package/board co-design.

BIO

Prof. Hideki Asai
Graduate School of Science and Technology, Shizuoka University

Hideki Asai received B.E., M.E. and Ph.D. degrees in electrical engineering from Keio University, Yokohama, Japan, in 1980, 1982 and 1985, respectively. In 1985, he was with the Department of Electrical and Electronics Engineering of Sophia University, Tokyo, Japan. Since 1986, he has been engaged in research at Shizuoka University mainly on VLSI-CAE, Parallel computing systems and Neural networks. He has received the research encouragement awards on Takayanagi anniversary, the 50th anniversary of the founding of IEICE Tokai branch and Saitoh anniversary, in 1988, 1989 and 1993, respectively. He was a secretary of IEEE Circuits & Systems Society Tokyo Chapter from 1994 to1995, and a secretary of Technical Group on Nonlinear Problem of IEICE from 1997 to 1999. He is now  a Professor of Shizuoka University, a visiting professor of Carleton University in Ottawa (Canada) and Santa Clara University in California (USA).