Abstract:

“1. Keynote Speech: “Automatic Partitioning of Behavioral Descriptions for High-Level Synthesis with Multiple Internal Throughputs”

C-based design is finally becoming a reality and most VLSI design teams have started adopting this methodology for some of their designs. The increase in productivity combined with the improvement in the quality of the results of commercial High-Level Synthesis (HLS) tools has convinced many to make the transition. This transition is nevertheless gradual and currently most of the applications being targeted are Digital Signal Processing (DSP) related. HLS has shown in the past that it can rival hand coded RTL designs for these type of applications and in some occasions even lead to much smaller designs due to its ability to maximize resource sharing. The nature of these DSP applications vary, but very often these have to be fully pipelined, where a given throughput is given as a constraint (i.e. Inputs’ Data Initiation Interval – DII) and the smallest possible design area wants to be achieved. In some cases a latency constraint is also specified and in other cases it is irrelevant. The main problem with these type of applications, with small DII (e.g. DII=1), is that they consume a large number of registers and do not allow much resource sharing. Moreover, in order to synthesize C descriptions in ‘fully pipelined mode’ severe restrictions apply to the input behavioral description e.g. loops should all be ‘unrollable’ and functions ‘inlined’. This limits the type of circuits that can be generated and restricts severely the design space that can be explored, which is one of the benefits of C-based design. This presentation focuses on the automatic partitioning of behavioral descriptions (C/SystemC) for pipelined applications, also called streaming applications, in order to minimize the total design area.

Keynote Speaker: Prof. Benjamin Carrion Schafer

Dr. Benjamin Carrion Schafer received the B.Eng. degree in Electrical and Electronic Engineering from the Polytechnic University of Madrid, Spain, the M.Sc. degree in Microelectronics from Birmingham City University, U.K., and FH-Darmstadt, Germany. After completing his Ph.D. at the University of Birmingham, U.K., he worked in the Computer Science Department at the University of California Los Angeles (UCLA) as a Postdoctoral Researcher from 2003 to 2004. He then joined the School of Electronic Engineering and Computer Science at Seoul National University, Korea, as a Visiting Research Scholar from 2005 to 2007. From 2007 until September 2012, he had been working as a Senior Researcher at System IP Core Department, Central R & D Centre, NEC Corporation, Kawasaki, Japan. Dr. Carrion Schafer has been engaged in the research and development of VLSI systems, reconfigurable computing, thermal-aware VLSI design and High Level Synthesis (HLS). He served on the TPC of CASES 2006 and as a committee member at the RECONFIG, DAC (user track) and ESLSyn conferences. He is also a member of OSCI’s (Accellera) SystemC synthesizable user group committee. He holds an MBA from McGill University.

“2. Basics of High Level Synthesis (Tutorial)”

This talk will cover the basic mechanism of High Level Synthesis and advantages of High Level Synthesis and High Level Verification. Technical reasons why HLS can generate smaller chip than RTL design will also be explained. In addition, it will go into how High Level Synthesis can increase design efficiency.

Speaker: Dr. Kazutoshi Wakabayashi : Senior Principal Researcher of Central Research Labs, NEC Corporation

Kazutoshi Wakabayashi received his B.E. and M.E. degrees and Ph.D from the University of Tokyo in 1984, 1986 and 2006 respectively. He was a visiting researcher at Stanford University from 1993 to 1994. He joined NEC Corporation in Kawasaki Japan in 1986 and he is currently a Senior Principal Researcher of the Central Research Labs at NEC Corporation. Dr. Wakabayashi has been engaged in the research and development of VLSI, CAD systems, high-level and logic synthesis, formal and semi-formal verification, system-level simulation, HDL, emulation, HLS and floorplan links, and reconfigurable computing. He has served on the executive/organizing committee for numerous prestigious international conferences. Positions include ASP-DAC’09 General Chair, CODES+ISSS’09 Co-Technical Program Chair, Secretary of Steering Committee of ASPDAC, and Executive Committee for ICCAD and DAC, Tutorial Chair of ASPDAC2006, Steering Committee of ITC-CSCC (09-). He has also served on the program committees for several international conferences such as DAC, ICCAD,DATE, ASP-DAC, ISSS, SASIMI, and ITC-CSCC, ISCAS, VLSI-TSI, SBCCI, VLSI Design, ESS, and ISLP.

“3. CyberWorkBench Technical Introduction”

CyberWorkBench is a best-in-class High Level Synthesis and High Level Verification tool used over 15 years for real chip design. CyberWorkBench provides “All-in-C” synthesis and verification: All types of modules (controllers and datapath) are synthesized from C and functional and timing verification can be done at the original C source code.
- Controller : Clock Notion, Cycle by Cycle Behavior (DMA Controller, Flash Memory Controller, Transmission Circuits, B/B)
- Complex Algorithmic Circuit Design : Face Recognition, High-End Encryption, Pipeline Circuits: Filters, ECC, DSP, Graphic Processing
- All-in-C Verification : Designer can debug not only functionality but also Timing (Cycle) on the C/SytemC with our Cycle Accurate Source Code Debugger.

“4. Success Stories”

Success stories from major electronics OEMs for control and data path circuits will be shown. The presentation will cover how these companies implemented CyberWorkBench into their design process to reduce time-to-market, gate size, and power consumption.

Speaker: Tetsuya Aoyama : Assistant Manager, NEC Informatec Systems

Tetsuya Aoyama received a BE degree in electronic engineering, and an MS degree in information sciences from Tohoku University, Sendai, Japan, in 2001 and 2003, respectively. He joined NEC Corporation, System Devices Research Laboratories in 2003. His research interests include low-power hardware design and high-level design methodology for VLSIs.

“5. CyberWorkBench Demo”

Demonstration of CyberWorkBench high level synthesis and verification tool. You will get to witness the key features of this powerful tool and the user friendly interface.

Time Table:
4:00 pm – 4:45 pm: “Automatic Partitioning of Behavioral Descriptions for High-Level Synthesis with Multiple Internal Throughputs (Keynote Speech)” by Prof. Benjamin Carrion Schafer
4:45 pm – 5:15 pm: “Basics of High Level Synthesis (Tutorial)” By Dr. Kazutoshi Wakabayashi
5:15 pm – 6:00 pm: “CyberWorkBench Technical Introduction/Success Story in Japan/Demo” by Tetsuya Aoyama

Event Registration:
*Pre-registration is required to attend the seminar

SIEMIC and TechDream are pleased to invite you to “EMC Design & Test Seminar,” an event which will take place on May 22nd (Wednesday) 9:30 am to 4:00 pm at SIEMIC, Milpitas CA. We are honored to have some of the industry’s most experienced experts as our guest speakers. This seminar is free to attend and lunch will be provided. Space is limited and registration is required.

Registration Click Here

*Pre-registration is required to attend the seminar

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1. “Reduce Noise and Improve Power Integrity with Embedded Capacitance Technology”

Abstract: Device data rates have increased tremendously in the late 2000s; especially since smart phone technology and other high speed devices hit the market. This change has forced companies that are processing the data to design and develop next generation chips, PCBs, and other architecture to meet the challenges of the new higher speed, high volume devices. With the increasing processing speeds, lower power delivery margins, and new design sets there have also been negative side effects. When traditional PCB design guidelines are used for these systems that are operated beyond 100 MHz there are significant resonances that occur at various frequencies. These are resonances starting within the PCB which could affect the whole system. This could also lead to noise, signal loss/distortion and EMI. One proven way to significantly reduce this resonance is to narrow the dielectric gap between the power and ground planes within the PCB. This presentation will cover the how you can improve PDN using embedded capacitance technology

Presenter: Bob Carter, Oak-Mitsui Technologies (Director of Technology and Business Development)

Over 27 years professional experience in the printed circuit, advanced electronic materials, and chip packaging industries. Spent extensive time supporting engineering, marketing, and sales, worldwide. Initiated the start-up of 2 PCB factories in China, Shenzhen and Suzhou. Led design, engineering, development, and applications organizations at companies such as Xerox, Toppan, Multi-Fineline Electronix (M-Flex), Rogers Corporation, Flex2Chip Inc. (Tessera), Matsushita/ Panasonic Electronic Materials, and Oak-Mitsui Technologies. Currently a Senior Technology Executive supporting Oak-Mitsui and FaradFlex Embedded Capacitance materials. Actively involved in technology leadership committees in the IPC, IEC, and IEEE.

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2. “Near-field Magnetic Probe Method Predicting Far-field Measurements “

Abstract: Traditional methods for measuring EMC and field density at the design stage can hamper the speed in which one determines the root cause of a problem and resolve the issue in real-time. APREL will present and demonstrate how precision measurements based on volumetric scans can approximate the far field of a discrete source of noise. This has been developed using a field approximation routine based on well documented principles. In the process of reducing spurious emissions or interference EMC engineers will use suppression techniques of shields, boxes and cages. These methods have been found to work in normal applications but as the frequency expands traditional methods of EMC suppression may not be as effective. The far field approximation technique presented, based on a published paper allows an engineer to test a sub assembly in the near field and then have a value which can be extrapolated to the far field. Measurements taken using the broadband near field “magnetic probe method” used with an automated scanning system (EM-ISight) can be extrapolated to either a 3m or 10m range space. Such a technique can allow the engineer to determine the effectiveness of their design prior to the final integration of an assembly thus understanding better the uncertainties of a previously developed reference design or suppression methods. This presentation will demonstrate how engineers can identify evanescent modes and determine if they will resonate at a harmonic further up in frequency and impact the integrity of a circuit design.

Presenter: Stuart Nicol, Aprel (CEO)

Stuart Nicol has worked within the field of high technology/telecommunications for over 16 years both in Europe and North America. He has been the lead in all major automated system development programs at APREL including SAR (Specific Absorption Rate). HAC (Hearing Aid Compatibility) and EM-ISight (near field scanning). He has held many positions within the international standards development committees and is the current chairman for the Canadian delegation of IEC TC-106, he received his degree in the United Kingdom (electronic and manufacturing engineering) and is the CEO of APREL.

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3. “Improve PCB Design: Eliminating EMI and Mitigating ESD”

Abstract: In order to improve your PCB design workflow, it is essential that you minimize EMI and ESD at early design stage.This presentation will cover how EMIStream, a tool developed by NEC, can help you detect EMI and ESD causing factors. A new feature where EMIStream can read in measurement data created by EM-ISight-2, an automated near-field scanning system, will also be introduced. The presentation will include a demonstration of the tool.

Presenter: Yoshi Fukawa, TechDream (President and Founder)

Yoshi Fukawa received his B.S. degrees in Electrical Engineering from Tokyo University of Science, Japan, in 1988. He received a certification of the NARTE EMC Engineer in 2000. He used to be an EMC committee member of the JEIDA in Japan. He currently is a member of the IEEE Santa Clara Valley EMC Chapter. He is a founder of TechDream who has been providing EMC/PI total solutions carrying EMI/PI simulation software.

Presenter: Eriko Yamato, TechDream (VP of Sales and Marketing)

Eriko received her Master of Arts Degree in Communication from Stanford University in 2002. She has 10-plus years of experience in business development and marketing of computer hardware/software, RF/Microwave products, and electronic components. She has been an active member of the IEEE EMC Santa Clara Valley Chapter since 2010 and currently serves as Chair.

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4. “Latest News on Basic RF immunity and Emission Standards”

Abstract:This presentation will cover recent developments with immunity and emission standards as well as the IEC committee structure. A must hear for EMC engineers who need to be up-to-date on standards.

Presenter: Randy Johnson, Teseq (Sales Manager)

Randy Johnson has been working in the EMC marketplace for over 30 years. He was co-owner of Loren Green Associates, a respected Manufacturer’s Rep company in Chicago, IL. Since 2004, Randy has been a Sales Manager at Schaffner Test Systems, now known as Teseq Inc. Randy was part of the management buyout of Teseq in 2007. Randy has been directly involved with customers in engineering/meeting their test equipment, systems & EMC software requirements for Commercial & Automotive applications.

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5. “Updating Older Anechoic Chambers to New Standards”

Abstract: There have been significant changes in EMC emissions and immunity measurement standards since the early 1990’s. At the same time anechoic materials have also evolved to meet the new requirements. Coupled with these changes, is the need to refurbish and update chambers, which are at the end of their expected performance capabilities. This presentation will discuss current options to meet the new standards and also considerations that will impact a successful project.

Presenter: Peggy Girard, Panashield (President)

Peggy joined Panashield in 1991 and has been a key contributor to the company’s growth and reputation for high quality and responsiveness. Formerly International Sales Director for Asia with Ray Proof Corporation for eight years, Peggy has more than twenty-nine years’ experience in RF shielding and anechoic chamber design and construction. Peggy has worked directly in both a sales and project management capacity with major International government agencies and companies in supplying turnkey RF/EMC facilities, including Intertek Testing Services, Cisco Systems, NASA Langley Research Center, IPTN Aircraft, Indonesia, Agency for Defense Development, Korea, Israeli Aircraft Industries, Hewlett Packard worldwide, Samsung and Hyundai Motor in Korea, Beijing Simulation Center, China, IBM in Brazil; Peggy is a graduate of Sweet Briar College in Virginia, with studies at University of Heidelberg, Germany and Salzburg University, Austria, with a B.A. Degree in German and International Affairs.

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6. “The EMC Engineer’s Toolkit: Tips and Tricks”

Abstract:In today’s fast-paced product development cycles, the pressure to compress testing and certification schedules is always increasing. Mistakes made in the testing process can have huge financial impacts if product releases are delayed as a result, or if flawed testing leads to later product recalls. Even the most experience EMC engineers can have the occasional oversight, which can become career-limiting events (CLE). Join Mark for a discussion of the major sources of EMC compliance testing pitfalls, managing risk, more efficient testing and report-writing techniques, and the danger of assumptions.

Presenter: Mark Maynard, SIEMIC, Inc. (Director of Marketing and Business Development)

Mark Maynard is the Director of Marketing and Business Development at SIEMIC, Inc., a leading compliance testing and certification company, with 9 global locations. At SIEMIC he is responsible for engineering consulting, working with regulatory industry groups, marketing, and training. Mark is also an elected member of the executive board of the Telecommunications Certification Body Council (TCBC). Mark holds two degrees from Texas State University, a BS in Pure Mathematics and Physics, and a BAAS in Marketing and Business. Mark was inducted as a Senior Member of the IEEE by the Central Texas EMC Society, is an iNARTE Certified Product Safety Engineer, and is also a certified Project Management Professional (PMP). Prior to SIEMIC, he worked for over 20 years at Dell, in international regulatory compliance and product certifications, with various positions including wireless/telecom certification engineer, EMC engineer, and product safety engineer. In 2008, Mark left Dell to pursue teaching mathematics and science at the university and high school levels, and this year returned to the regulatory compliance field by joining SIEMIC, Inc.

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Event Registration Here

*Pre-registration is required to attend the seminar

Schedule:

 9:00 to  9:30 AM    Check in
 9:30 to  9:40 AM    Opening Introduction
 9:40 to 10:40 AM   Reduce Noise and Improve Power Integrity with Embedded Capacitance Technology
10:40 to 11:25 AM  Near-field Magnetic Probe Method Predicting Far-field Measurements
11:25 to 11:55 AM  Improve PCB Design: Eliminating EMI and Mitigating ESD
11:55 to 12:20 PM  EMI Suppression and ESD Rule Checker Tools Demonstration
12:20 to  1:30 PM   Lunch Break & Lab Tour (Lunch provided)
 1:30 to  2:00 PM   Teseq
 2:00 to  2:30 PM   Updating Older Anechoic Chambers to New Standards
 2:30 to  2:45 PM   Coffee Break
 2:45 to  3:45 PM   The EMC Engineer’s Toolkit: Tips and Tricks
 3:45 to  4:00 PM   Q & A